1. Field of the Invention
The present invention relates to a semiconductor memory, particularly relates to a dynamic random access semiconductor memory (DRAM) in which a row address and a column address can be latched by a 2-cycle clock signal using a relatively low-speed clock frequency and which enables paging operation.
2. Description of the Related Art
Dynamic RAM (DRAM) which is one of semiconductor memories writes or reads information depending upon whether electric charge is stored in a capacitor or not and has a problem that as electric charge gradually decreases after writing. Therefore, refresh, that is, the operation of reading information and rewriting it is required every a few millisecond and a circuit is complex.
Referring to the drawings, an example of the circuit operation of conventional type DRAM will be described below. In this example, DRAM is composed of MOSFET as a switching transistor and a capacitor. The gate electrode on MOSFET is connected to a word line, one of the source and the drain is connected to a bit line, the other i s connected to one electrode of the capacitor and electric charge in the capacitor is detected by a sense amplifier by controlling the potential of the word line and the bit line in synchronization with a clock pulse.
FIGS. 11A and 11B are timing charts showing the input/output of data to/from conventional type DRAM disclosed in JP-A-11-149767, FIG. 11A shows read operation and FIG. 11B shows write operation. As shown in FIG. 11A, in read operation, first, a circuit for a row address which is in a precharge state is activated by turning /RAS (a row address strobe) which is a second clock pulse to a trailing edge at the leading edge of CLK which is a first clock pulse, storage operation is started and a row address is latched. Hereby, a memory cell connected to a selected word line is activated and a sense amplifier connected to a selected bit line pair is activated.
Next, read operation is started by turning /CAS (a column address strobe) which is a third clock pulse to a trailing edge at the next leading edge of CLK which is the first clock pulse and a column address is latched. At this time, potential difference read in a bit line pair to which a selected memory cell is connected is amplified by turning a write enable signal /WE at a high level and disabling writing, effective data is determined and is further output to an external device via a read amplifier and others. Further, a circuit for a row address is turned in a precharge state by turning /RAS and /CAS at a high level at the next leading edge of CLK which is the first clock pulse and the next operation gets ready.
In the meantime, as shown in FIG. 11B, in write operation, /RAS is also similarly turned to a trailing edge at the leading edge of CLK which is the first clock pulse and a row address is latched. Hereby, a memory cell connected to a selected work line is activated and a sense amplifier connected to a selected bit line pair is activated. /CAS is turned to a trailing edge at the next leading edge of CLK which is the second clock pulse and a column address is latched. At this time, a write enable signal /WE is turned at a low level, write operation is enabled and effective data to be stored in a selected memory cell is input from a write amplifier and others. Further, a circuit for a row address is turned in a precharge state by turning /RAS and /CAS at a high level at the next leading edge of CLK which is the first clock pulse and the next operation gets ready.
In this specification, a mark added before a signal name, xe2x80x9c/xe2x80x9d denotes inversion and denotes a signal turned in an active state when the signal is at a low level (low active).
However, as such conventional type DRAM requires three cycles of RAS, CAS and a precharge cycle in reading and writing, a high operating frequency is required and power consumption is increased. Particularly, in case the operating frequency of DRAM determines the frequency of a system, a problem occurs.
The invention is made to solve the problems of the conventional type and realizes a semiconductor memory that can be operated at a low frequency without lowering data transfer rate.
To achieve the object, the invention is configured so that a series of operation can be completed by two clock pulses of a row address strobe and a column address strobe for operating DRAM.
Concretely, a semiconductor memory according to the invention provided with a memory cell array including plural memory cells, plural word lines selected according to a row address signal from an external device, plural bit lines selectively activated according to plural column address signals from the external device and a sense amplifier that amplifies data read every plural bit lines is characterized in that row address latch means that latches a row address signal corresponding to the activated state of a first control signal triggering a first edge of a clock pulse, sense amplifier activation means that activates the sense amplifier after a predetermined period determined by internal circuit operation since the first edge elapses corresponding to the activated state of the first control signal, column address latch means that latches a column address signal according to the activated state of a second control signal and precharge signal generation means that generates a precharge signal for precharging the bit Line after the predetermined period determined by the internal circuit operation since a second edge according to the activated state of the second control signal are provided.
As a second aspect of the invention, a semiconductor memory according to a first aspect is characterized in that the first and second edges mean edges where a clock pulse is turned from a first level to a second level, a clock pulse and first and second control signals are respectively input from an external device and control means that determines a state of a writing control signal for controlling whether data is written in the memory cell or not triggering the second edge, enables write operation in case the result of the determination is in a first state and enables read operation in case the result of the determination is in a second state different from the first state is provided.
As a third aspect of the invention, a semiconductor memory according to the first aspect is characterized in that timing control means that determines a state of the first control signal triggering the second edge, disables page mode operation in case the result of the determination is in the first state, enables precharge in the bit line in a clock cycle including the second edge to get ready for the next operation, enables page mode operation in case the result of the determination is in the second state different from the first state and disables precharge in the bit line in the clock cycle including the second edge is provided.
As a fourth aspect of the invention, a semiconductor memory according to the first aspect is characterized in that the first and second edges are edges where a clock pulse is turned from the first level to the second level, a function for setting a third control signal to the first state triggering the second edge and setting the third control signal to a second state different from the first state when read operation or write operation is finished is provided and precharge in the bit line is started after a predetermined period since the third control signal is set to the second state.
As a fifth aspect of the invention, a semiconductor memory according to the fourth aspect is characterized in that further, plural read/write amplifiers arranged between the sense amplifier and a data input/output circuit that read/write data from the sense amplifier and a column control circuit that controls the read/write amplifier are provided, the column control circuit generates a read/write amplifier control signal for controlling the operation of the read/write amplifier according to the activated state of a second control signal triggering the second edge, the read/write amplifier control signal is returned to the column control circuit via the read/write amplifier that receives a signal latest of the plural read/write amplifiers and a third control signal is set to the second state according to the read/write amplifier control signal returned to the column control circuit.
As a sixth aspect of the invention, a semiconductor memory according to the first aspect is characterized in that further, an internal clock for activating the sense amplifier, a first internal clock generator that turns the internal clock in a predetermined state triggering a first edge of a clock pulse corresponding to the activated state of a first control signal after a predetermined period elapses since the first edge and a second internal clock generator that latches the first control signal in synchronization with the clock pulse are provided, the first internal clock generator is connected to the internal clock via a first fuse element, the second internal clock generator is connected to the internal clock via a second fuse element and the first fuse element or the second fuse element can be disconnected during the manufacturing process or after the manufacture if necessary.
As a seventh aspect of the invention, a semiconductor memory according to the sixth aspect is characterized in that a connected state of the first fuse element or the second fuse element is determined by an option of a lithographic mask used in a wiring process.